Dear Ankit,

Extremely Sorry for the delayed response.

Please rename your file and module to "dflipflop"as the name d_FF is not getting accepted by KiCAD-NgSpice converter. I have made some changes to the code please see below:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-----------------------
entity dflipflop is
Port(
Din : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Qbar : out std_logic
);
end dflipflop;

library ieee;
use ieee.std_logic_1164.all;
entity nandgate is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end nandgate;

architecture e1 of nandgate is
begin
y <= a nand b;
end e1;

library ieee;
use ieee.std_logic_1164.all;

entity notgate is
port(
a: in std_logic;
y: out std_logic
);
end notgate;

architecture e2 of notgate is
begin
y <= not a;
end e2;

architecture structural of dflipflop is
component nandgate
port( a : in std_logic;
b : in std_logic;
y : out std_logic
);
end component;

component notgate
port( a : in std_logic;
y : out std_logic
);
end component;

signal w1,w2,w3,w4,w5,w6,w7 : std_logic;
begin
u1 : nandgate port map(Din,Clk,w1);
u2 : notgate port map(Din,w2);
u3 : nandgate port map(Clk,w2,w3);
u4 : nandgate port map(w1,w7,w6);
u5 : nandgate port map(w3,w6,w7);
Q<=w6;
Qbar<=w7;
end structural;

Please see the attached output and the schematic for your reference.

Thank You.

Regards,
Sumanto Kar
eSim Team