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your circuit contains unknown model...

i created D flip-flop using structural VHDL code , using NGHDL feature of esim, but while converting KIcadtoNGSPICE , it is showing "your circuit contains unknown model D_FF" and hence i cannot simulate my circuit. please help me ASAP... i am also adding my vhdl code here... pleae look...

~~~~~~~~~~~~~~~~D_FF.vhdl~~~~~~~~~~~~~~~~

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-----------------------
entity d_FF is
Port(
Din : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Qbar : out std_logic
);

end d_FF;

library ieee;
use ieee.std_logic_1164.all;

entity nandgate is
port(
a : in std_logic;
b : in std_logic;
y : in out std_logic
);
end nandgate;

architecture e1 of nandgate is
begin
y <= a nand b;
end e1;

library ieee;
use ieee.std_logic.all;

entity notgate is
port(
a: in std_logic.all;
y: out std_logic.all
);
end notgate;

architecture e2 of notgate is
begin
y <= not a;
end e2;


architecture structural of d_FF is

component nandgate
port( a : in std_logic;
b : in std_logic;
y : out std_logic
);
end component;

component notgate
port( a : in std_logic;
y : out std_logic
);
end component;

signal w1,w2,w3,w4,w5 : std_logic;

begin

u1 : nandgate port map(Din,Clk,w1);
u2 : notgate port map(Din,w2);
u3 : nandgate port map(Clk,w2,w3);
u4 : nandgate port map(w1,Qbar,Q);
u5 : nandgate port map(w3,Q,Qbar);

end structural;


eSim 26-08-21, 1:01 a.m. ankitbanjare@esim
0

I faced similar kind of issue last time, I am still searching for some proper solution Same issue still no fix to this. mcdvoice survey

24-09-21, 12:35 p.m. Macejkovic


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