NGspice simulation error....

while simulating DFLIP-FLOP( created by nghdl feature of esim using VHDL code) it is not showing output as compared to standard truth-table of D'Flip-FLop(see image below),please help me to solve this problem ASAP. i am also adding my VHDL code of d-flip-flop here..........

library ieee;
use ieee.std_logic_1164.all;

entity dff is 
port (data : in std_logic;
	clk : in std_logic;
	reset : in std_logic;
	q : out std_logic);
end dff;

architecture Behavioral of dff is
	process (clk) begin
		if (reset = '1') then 
		q <= '0';
		elsif (rising_edge(clk)) then
		q <= data;
		end if;
	end process;
end Behavioral;


eSim 21-07-21, 11:17 p.m. ankitbanjare@esim
esim terminal screenshort---
21-07-21, 11:19 p.m. ankitbanjare@esim

schematic for simulation of Dflip-flop......
21-07-21, 11:21 p.m. ankitbanjare@esim


Damm even I am having a similar kind of issue, I have searched all over the internet and even have posted on number of threads on different forum, no solution seems to work. I am really frustrated, can anyone of you here help me resolve this issue, I am very much tired now. get-vidmate.com instasave

23-07-21, 6:59 p.m. carterashley


I think I need to use the small signal analysis in ngspice, though I'm really only interested in the voltage and/or current phasors. Is that even possible with ngspice? Perhaps a bit more concrete:

  • Can ngspice do what I'm trying to do?
  • If it can, where can I find examples of analysis of such a circuit with ngspice? I'd prefer to use barebones ngspice without a GUI on top of it.
  • Lastly, are there any circuit analysis books that use/teach ngspice alongside their regular content?




16-08-21, 11:52 a.m. Stracke


The D-Flip Flop is an implementation of a dual-rail to single rail (D/S) flip flop. The D/S flip flop is a simple combinational circuit in which the output, Q, is the inverse of the input, D. The figure below shows a diagram of the standard truth table of a D/S flip flop. The dual-rail to single rail (D/S) flip flop can be implemented using three different standard logic gates: an XOR gate, an XNOR gate, and an XNOR gate with inverted inputs. The figure below shows a diagram of these 3 implementations. The NAND gate implementation shown in Figure 9 can be made more efficient by merging two NAND gates into one NAND2 gate and by adding inverters to make both inputs to the NAND2 gate active high (A). www.tcswebmail.info www.upsers.fyi www.prepaidgiftbalance.fyi

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