NGspice simulation error....

while simulating DFLIP-FLOP( created by nghdl feature of esim using VHDL code) it is not showing output as compared to standard truth-table of D'Flip-FLop(see image below),please help me to solve this problem ASAP. i am also adding my VHDL code of d-flip-flop here..........

library ieee;
use ieee.std_logic_1164.all;

entity dff is 
port (data : in std_logic;
	clk : in std_logic;
	reset : in std_logic;
	q : out std_logic);
end dff;

architecture Behavioral of dff is
	process (clk) begin
		if (reset = '1') then 
		q <= '0';
		elsif (rising_edge(clk)) then
		q <= data;
		end if;
	end process;
end Behavioral;


eSim 21-07-21, 11:17 p.m. ankitbanjare@esim
esim terminal screenshort---
21-07-21, 11:19 p.m. ankitbanjare@esim

schematic for simulation of Dflip-flop......
21-07-21, 11:21 p.m. ankitbanjare@esim


Damm even I am having a similar kind of issue, I have searched all over the internet and even have posted on number of threads on different forum, no solution seems to work. I am really frustrated, can anyone of you here help me resolve this issue, I am very much tired now. get-vidmate.com instasave

23-07-21, 6:59 p.m. carterashley

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