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Error While creating digital model using NGHDL feature.

while creating digital model of universal-shift-register using NGHDL feature of esim, having an error "valueError : invalid literal for int() with base 10: 'ir'"(see image below) ,and does not able to create digital model of shift register. i am also adding my VHDL code here please go through it and Respond ASAP.

~~~~~Univ_shiftreg.vhdl~~~~~~~~~~~~

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;


entity univ_shiftreg is
port(clk, il, ir : in std_logic;
	s : in std_logic_vector(1 downto 0);
	i : in std_logic_vector(3 downto 0);
	q : out std_logic_vector(3 downto 0));
end univ_shiftreg;
architecture Behavioral of univ_shiftreg is 
	signal qtmp : bit_vector(3 downto 0);
begin
process(clk)
begin 

if (clk = ‘1’  and clk’event) then 
case s is
when “00” => qtmp <= qtmp;
when “01” => qtmp <= i ;
when “10” => qtmp<=qtmp(2 downto 0) & ir;
when “11” => qtmp<= il & qtmp(3 downto 1);
when others => null;
end case;
end if;
end process;
q <= qtmp;
end Behavioral;

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~


eSim 19-07-21, 10:03 p.m. ankitbanjare@esim
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Dear Ankit, Please do not use comma in port declaration. You need to declare each port separately. Please find the corrected code below:
Library ieee;
use ieee.std_logic_1164.all;



entity univ_shiftreg is
port(
clk : in std_logic;
il : in std_logic;
ir : in std_logic;
s : in std_logic_vector(1 downto 0);
i : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0));
end univ_shiftreg;
architecture Behavioral of univ_shiftreg is
signal qtmp : bit_vector(3 downto 0);
begin
process(clk)
begin

if (clk = ‘1’ and clk’event) then
case s is
when “00” => qtmp <= qtmp;
when “01” => qtmp <= i ;
when “10” => qtmp<=qtmp(2 downto 0) & ir;
when “11” => qtmp<= il & qtmp(3 downto 1);
when others => null;
end case;
end if;
end process;
q <= qtmp;
end Behavioral;
25-07-21, 3:33 p.m. Sumanto


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