While creating a digital model using NGHDL feature of esim, after uploading VHDL code it shows -- "list index out of range"(see image below), basically I am working on ARITHMETIC UNIT

but it shows this error. also I am adding my vhdl code here , please look and help me ASAP.....

~~~~~~~ARTHMETIC_BLOCK.vhdl~~~~~~~

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity au is
port(a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in STD_LOGIC;
sel : in std_logic_vector(3 downto 0);
y : in std_logic_vector(31 downto 0)
);
end au;
architecture Behavioral of au is
Signal arith : std_logic_vector(31 downto 0);
begin

~~~~~~~~~~~~~~Arithmetic_unit~~~~~~~~~~~~~~~~~
with sel (2 downto 0) SELECT
arith <= a When "000" ,
a+1 when "001",
a-1 when "010",
b when "011",
b+1 when "100",
b-1 when "101",
a+b when "110",
a+b+cin when "111";
end Behavioral ;

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