Scilab - facing problems with designing a counter

facing problems with designing a counter

1.I am facing problems in simulating an up down counter built using jk-flip flops in xcos. The problem is that simulation never actually takes off. I have built a 12 bit counter and used scilab 5.5.2. All the packages are in place. Is there a way to make it work?

2. Can I get a model of an VCO?

Scilab 05-03-21, 12:40 p.m. gary36

This question shows research effort; it is useful and clear

This question does not show any research effort; it is not useful and unclear

I faced similar kind of issue last time, I am still searching for some proper solution Same issue still no fix to this.

07-04-21, 1:36 p.m. WiltonFaison

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