

facing problems with designing a counter
1.I am facing problems in simulating an up down counter built using jk-flip flops in xcos. The problem is that simulation never actually takes off. I have built a 12 bit counter and used scilab 5.5.2. All the packages are in place. Is there a way to make it work?
2. Can I get a model of an VCO?
Scilab


I faced similar kind of issue last time, I am still searching for some proper solution Same issue still no fix to this.


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