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Critical Path Delay
Hello,
How can I find the critical path delay of a digital circuit? Please also advise that how can I make subplots on a single window?
eSim
0You can look at this for critical path calculations : http://www-inst.eecs.berkeley.edu/~cs150/sp13/agenda/lec/lec17-timing2.pdf
Subplots on a single window can be obtained by modifying the cir.out file -> if you wish to see plots of node a, b, con a single plot window, type plot v(a) v(b) v(c) after print alli > plot_data_i.txt line in the cir.out file
Dear Sir,
Thank you for your response. I studied your advised pdf. but there is not mentioned about the critical path delay calculation using eSim. I'm very sorry, may be there is a mis-understanding in asking a question but my question was; how can I find the critical path delay of a circuit using eSim?
Thank you.
29-04-20, 3:41 p.m. Namra_Riaz
It seems to me that critical path delay is something that is usually concerned when you are executing or planning the layout design of a chip to be fabricated on Silicon. The logic you wish to implement inside chip maybe simulated in eSim although eSim does not offer features that can be faciliated directly for synthesis of a HDL code or even layout for that matter.
29-04-20, 3:56 p.m. Saurabhb17
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