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Getting errors when simulating the basic logic gates
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Sir/Madam,

Where can I read about simulating basic logic \r\ngates using eSim. We tried out simulating using the "d_inverter" component\r\n from "eSim_Digital" library and the "pulse" source from the \r\n"eSim_Sources" library. But during simulation we get the error "Error \r\nwhile opening the python plotting Editor". I am sure we have made some \r\nmistake in the schema or may be while entering the values for the \r\n"pulse" component. Would you kindly look at the .cir file below and help\r\n us to solve the problem. We will also be very grateful if you kindly \r\nsend us some tutorials on simulating digital circuits.

Best regards,
Arup Baruah.

The .cir file:

* /home/abaruah/Work/eSim/Workspace/Test06/Test06.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jan 18 12:57:10 2016

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
U1 Net-_U1-Pad1_ GND d_inverter
v1 Net-_U1-Pad1_ GND pulse

.end

The .cir.out file:

* /home/abaruah/work/esim/workspace/test06/test06.cir

* u1 net-_u1-pad1_ gnd d_inverter
v1 net-_u1-pad1_ gnd pulse(0 1 0 0 0 1 1)
a1 net-_u1-pad1_ gnd u1
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u1 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end


eSim 18-01-16, 1:23 p.m. abaruah

Answers:

0

Hi,

Please see the answer at http://forums.fossee.in/question/72/simulation-of-basic-logic-gates/


18-01-16, 6:32 p.m. fahim


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